The invention relates to a synchronization apparatus and to a method for data synchronization.
Increasing data transmission rates is a fundamental aim of development for semiconductor apparatuses such as DRAMs (Dynamic Random Access Memories). Besides increasing clock rates, transmitting a plurality of data packets per clock cycle is also an option for increasing the data transmission speed. In a DDR-DRAM (Double Data Rate DRAM), for example, it is possible to transmit two data packets per clock cycle which are respectively synchronized to the rising and falling edges of the clock cycle.
It would be desirable to have a synchronization apparatus and a method for data synchronization which allow improved data transmission rates.